1. Field of the Invention
The present invention relates to a memory circuit for writing and reading data with the use of a non-volatile memory element.
2. Description of the Related Art
A conventional memory circuit is described with reference to FIG. 9. FIG. 9 is a schematic diagram of a memory cell structure in which a memory element for writing and a memory element for reading share a single floating gate.
In writing operation, a transistor Q1 is controlled to turn OFF and a transistor Q2 is controlled to turn ON. A write control circuit 92 applies a voltage between a source and a drain of an N-channel non-volatile memory element Q4 to inject electrons into a floating gate, thereby writing apiece of data in the non-volatile memory element Q4. N-channel non-volatile memory elements Q3 and Q4 are arranged to share a control gate indicated by a solid line and a floating gate indicated by a broken line. Thus, when the piece of data is written in the non-volatile memory element Q4, the data is also written in the non-volatile memory element Q3.
In reading operation, the transistor Q1 is controlled to turn ON and the transistor Q2 is controlled to turn OFF. A sense amplifier 91 applies a voltage between a source and a drain of the non-volatile memory element Q3 to detect whether the non-volatile memory element Q3 turns ON or not, and sends the result of detection as an output (see, for example, Japanese Published Patent Application No. H 04-079271).